Falcomm
NewIntroduced with GlobalFoundries at IMS 2026

GaNdalph.ai

GaNdalph.ai designs RF power amplifiers with proprietary foundation models trained on process-aware data developed alongside GlobalFoundries. A months-long design cycle can be reduced to minutes on GF RFGaN1.

Get early accessHow it works
gandalph.ai: new design
specTwo-stage K-band PA, 36 dBm Psat, 45% PAE target, GF RFGaN1
Searching the design space on GF RFGaN1...
Design ready
Topology
Two-stage GaN
Node
GF RFGaN1
Output
Layout-ready design
Time
About 90 seconds

Representative flow. Actual output depends on the spec.

Describe the spec✦Months reduced to minutes✦GF RFGaN1 qualified✦Purpose-built foundation models✦Layout-ready output✦Developed alongside GlobalFoundries✦Describe the spec✦Months reduced to minutes✦GF RFGaN1 qualified✦Purpose-built foundation models✦Layout-ready output✦Developed alongside GlobalFoundries✦

Foundation models trained on real process data.

GaNdalph automates power amplifier design using AI-augmented foundry PDKs. Its foundation models are trained on process-aware data developed alongside GlobalFoundries, capturing metal-stack EM physics, transistor nonlinearities, and manufacturability rules.

Falcomm built GaNdalph to expand what RF engineers can accomplish.

90 s
a first design
6–9 mo
traditional design cycle
RFGaN1
first supported GF node
See how it works
Macro photograph of a Falcomm Dual-Drive die seated on an evaluation board

What it handles end to end.

You describe the amplifier you need. GaNdalph does the rest of the flow, all the way to a layout you can hand to the fab.

Design

Custom chips on demand

  • Describe exactly the PA you need, in plain specs
  • One-stage or two-stage topologies
  • Band, output power, and efficiency targets
GaNdalph.ai wizard mascot holding an RF chip
Architecture

Topology selection

  • The models pick the architecture that fits the spec
  • The search starts from your target specifications
Matching

Built-in matching networks

  • Matching synthesis is integrated into the search
  • Networks are tuned against the foundry metal stack
Devices

Automatic transistor sizing

  • Device sizes are chosen against the foundry PDK
  • Sizing is grounded in device physics
Falcomm Dual-Drive QFN package shown from above and below, cut out on transparency
Layout

Zero-click layout

  • Layout is generated straight from the optimized schematic
  • Manufacturability rules respected the whole way through
Falcomm evaluation board photographed on a transparent background
Optimization

Trade-space optimization

  • Push on power, efficiency, or bandwidth and see the tradeoffs
  • Compare candidate designs side by side before committing
  • Select the version tuned to your system
Falcomm Dual-Drive QFN package seated on an evaluation board, photographed up close
[ How it works ]

How a design happens in three steps

Every GaNdalph design moves through the same three steps, from spec to a layout-ready result on a qualified GF node.

01

Describe the spec

Enter the band, output power, and efficiency target you need.

02

The models search the design space

GaNdalph's foundation models search that space against GF RFGaN1's process rules for a design that meets the spec.

03

Manufacturable, layout-ready output

The result is a layout-ready design on a qualified GF node.

Get early access →

Built around a qualified foundry process.

GaNdalph designs against GlobalFoundries process data and manufacturability rules. RFGaN1 is the first supported process, with additional GF nodes planned.

GF RFGaN1

Supported today

GlobalFoundries has qualified RFGaN1 for high-volume production. GaNdalph uses process-aware data developed alongside GF to keep its output grounded in that manufacturing process.

Falcomm K-band GaN evaluation board with Southwest connectors, cut out on transparency
PlannedGF 45RFSOI

The silicon-on-insulator process behind much of today's 5G and mmWave front-end hardware.

PlannedGF 22FDX

GF's FD-SOI platform, for designs that put RF and digital on the same piece of silicon.

PlannedGF 130NSX

GF's high-frequency platform for mmWave and radar front ends.

Built by the engineers who ship the silicon.

Falcomm's PA designers built GaNdalph from the process knowledge used across the company's product work.

Falcomm Dual-Drive QFN package seated on an evaluation board, photographed up close

Dual-Drive technology

GaNdalph's process knowledge builds on Falcomm's patented Dual-Drive PA architecture, the same technology behind the parts in our catalog.

Falcomm K-band GaN evaluation board with gold RF launches and Southwest Microwave connectors

The silicon

See the measured parts Falcomm ships today, including the GaN and CMOS PAs in stock now.

Falcomm and GlobalFoundries at IMS 2026.

GaNdalph debuted at IMS 2026 in Boston with first-class support for GF RFGaN1.

GaNdalph.ai | Falcomm